METHOD OF FORMING INTERCONNECTION

PURPOSE:To provide a formation method of an interconnection which is flattened by making use of the advantage of a self-alignment contact method. CONSTITUTION:A gate electrode 13 and an offset SiO2 film 14 are formed. After that, an interlayer insulating film 16 is formed, and an interlayer film 17...

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Bibliographic Details
Main Author UMEBAYASHI HIROSHI
Format Patent
LanguageEnglish
Published 02.02.1996
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE:To provide a formation method of an interconnection which is flattened by making use of the advantage of a self-alignment contact method. CONSTITUTION:A gate electrode 13 and an offset SiO2 film 14 are formed. After that, an interlayer insulating film 16 is formed, and an interlayer film 17 acting as the stopper of a wet etching operation is formed on it. A reflow film 18 is formed on the interlayer film 17, a resist 19 is patterned, and the reflow film 18 is isotropically worked by a wet etching operation, and a contact hole 20 is then made by an anisotropic etching operation. Thereby, parts other than the contact hole are flattened, and a problem in a working operation such as a short circuit or the like between upper-layer interconnections is solved.
Bibliography:Application Number: JP19940163482