TIMING SYNCHRONIZING METHOD OF IC TESTING DEVICE

PURPOSE: To synchronize expectation value data with read data by a method wherein a designated address and write data are inputted to an IC to be measured and a test pattern based on the data is read in accordance with the address to be compared with the expectation value data, then pass/fail data i...

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Bibliographic Details
Main Authors IWAGAMI KOYO, FUKUZAKI TADASHI
Format Patent
LanguageEnglish
Published 22.10.1996
Edition6
Subjects
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Summary:PURPOSE: To synchronize expectation value data with read data by a method wherein a designated address and write data are inputted to an IC to be measured and a test pattern based on the data is read in accordance with the address to be compared with the expectation value data, then pass/fail data is obtained by judging the result, thereby inspecting a characteristic of the IC. CONSTITUTION: An IC testing device tests an IC to be measured such as synchronous PRAM that outputs read data to a designated address by delaying several cycles. A test signal generating means 54 generates the test signal such as the designated address, read data, expectation value data and the like. A read/ write control means writes a test pattern based on the designated address and read data to the IC to be measured and reads it therefrom in accordance with the designated address. A judging means 62 compares the expectation value data with read data to judge the result and to output pass/fail data. A synchronizing means supplies the expectation value data to the judging means 62 by delaying it by a period of time corresponding to the number of cycles.
Bibliography:Application Number: JP19950301987