MICROPROCESSOR

PURPOSE: To shorten time to be required for an MPU stop request up to an MPU operation stop. CONSTITUTION: When a flag for permitting/inhibiting the generation of a cache flash signal is '1', a cache flash circuit generates a cash flash signal FLS when a clock is raised twice after inactiv...

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Bibliographic Details
Main Authors ARAI KOJI, TOMATSURI HIDEAKI, ISE HISAO, FUJIYAMA HIROYUKI
Format Patent
LanguageEnglish
Published 16.07.1996
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE: To shorten time to be required for an MPU stop request up to an MPU operation stop. CONSTITUTION: When a flag for permitting/inhibiting the generation of a cache flash signal is '1', a cache flash circuit generates a cash flash signal FLS when a clock is raised twice after inactivating a sleep signal supplied from the external and supplies the signal FLS to the clear input terminals CLR of respective valid flags V1 to Vn through respective transfer gates 61 to 6n. When the contents L1D to LnD of lock flags corresponding to the valid flags V1 to Vn are a value '0' indicating a rewrite permission, the gates 61 to 6n are opened. The cache flash circuit generates the signal FLS also at the time of executing an MPU stop instruction or a cache flash instruction.
Bibliography:Application Number: JP19940329139