IMAGE PROCESSOR

PURPOSE: To reduce the cost of the image processor by allowing image processing sections to process images in parallel and using a delay device at a lowermost speed to delay data to compensate a difference between required processing times when the image data transfer period after the processing is...

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Bibliographic Details
Main Author YAMADA HIROICHI
Format Patent
LanguageEnglish
Published 31.05.1996
Edition6
Subjects
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
ELECTROGRAPHY
ELECTROPHOTOGRAPHY
HOLOGRAPHY
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
MAGNETOGRAPHY
PHOTOGRAPHY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
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Summary:PURPOSE: To reduce the cost of the image processor by allowing image processing sections to process images in parallel and using a delay device at a lowermost speed to delay data to compensate a difference between required processing times when the image data transfer period after the processing is shorter than that before the processing. CONSTITUTION: The required processing time of a 1st image processing section 650 is shorter than that of a 2nd image processing section 660 by 3-lines + 5 picture elements. As a result, a data delay section 640 is provided to the input of the processing section 650 to compensate the difference by the image processing section 160. Delay object data D620b are transferred sequentially to FIFO memories ME1-ME3 in the delay section 640. The image data D620b from a line delay section 641 are delayed by 5 period times of a picture element clock signal SYNCK and the resulting image data D620b are fed to the 1st image processing section 650. The data delay section 640 is provided to the input side of the 1st image processing section 640 to allow the device operated by the picture element clock SYNCK and the cost of the data delay section 640 is reduced more than the case with the setting up of the delay section 640 to the output side.
Bibliography:Application Number: JP19940276352