TEST CIRCUIT FOR RELIABILITY TEST OF SEMICONDUCTOR MEMORY DEVICE

PURPOSE: To shorten the test time of a memory cell by connecting every test transmission line which is charged up to a prescribed voltage level to a bit line and sensing the voltage change of the test transmission line. CONSTITUTION: The test transmission lines NO1 and NO2 are charged via a charging...

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Bibliographic Details
Main Author CHIYOU TAISEI
Format Patent
LanguageEnglish
Published 12.09.1995
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TESTING
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Summary:PURPOSE: To shorten the test time of a memory cell by connecting every test transmission line which is charged up to a prescribed voltage level to a bit line and sensing the voltage change of the test transmission line. CONSTITUTION: The test transmission lines NO1 and NO2 are charged via a charging circuit 3636 before the test data DIN and -DIN are read out, and the data DIN and -DIN are written. Then a bit line connection control circuit 34 produces a connection control signal to control a bit line connection circuit 32, and the bit lines BL and -BL are connected to the lines NO1 and NO2. Then the voltage changes of both lines NO1 and NO2 are sensed for detection of a failure. Therefore, the test result is outputted with no intervention of a column gate as long as a test circuit of such a constitution is used. Thus, all memory cells connected to a relevant word line are simultaneously checked via a single enable state of the word line.
Bibliography:Application Number: JP19940327856