MOS TYPE TRANSISTOR

• Main Author: SAITO TATSU
• Format: Patent
• Language: English
• Published: 05.09.1995
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To improve breakdown strength at the time of avalanche without increasing ON resistance by diffusing impurities having the reverse conductivity forming action into the central part of a channel diffusing region at the central part of a unit cell structure, and enhancing the electric field of the central part of a p-n junction. CONSTITUTION:An n<+> well layer 8 is formed by the diffusion of donor impurities from the surface of an n<+> silicon substrate l. Then, polycrystalline silicon is deposited on the surface through an oxide film. The silicon is patterned so that the n<+> well 8 comes to the intermediate part of a gate electrode 6 comprising the polycrystalline silicon. When a p-type channel region 2 is formed by the diffusion of acceptor impurities with the gate electrode 6 as a mask, the p-n junction is curved to the surface side at the part of the n<+> well 8, wherein the donor impurities are diffused. Therefore,the voltage drop directly beneath a source region by the inflow of the avalanche current from the peripheral part of the channel diffused region is prevented by making the avalanche current flow into the wide area part at the center. Thus, the avalanche breakdown strength can be improved without increasing the ON resistance.