FRAME ALIGNER

• Main Author: IIZUKA EIJI
• Format: Patent
• Language: English
• Published: 24.01.1995
• Edition: 6
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; MULTIPLEX COMMUNICATION; PICTORIAL COMMUNICATION, e.g. TELEVISION; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To increase the margin to the jitter and the wander by providing plural delay amount and approach inhibition ranges, and selecting an optimal delay amount in accordance with a delay state and an approach state of a read-out timing of an elastic store. CONSTITUTION:Delay circuits 2-5 for delaying write data and a write frame pulse of an elastic store 1 by two kinds of delay amounts, respectively are provided, and selectors 6, 7 switch output signals of these delay circuits. Subsequently, the elastic store 1 sets an output signal of the selector 6 as write data, and sets an output signal of the selector 7 as a write timing. Also, approach inhibition range generating circuits 8, 9 generate an approach inhibition range before or after a read-out timing of the elastic store 1, a fact that the write timing of the elastic store 1 approaches these approach inhibition ranges is detected by phase comparators 10, 11, and by switching the selectors 6, 7 by its output information, an optimal signal is selected.