MULTI-BUS SYSTEM

PURPOSE:To reduce the loss time of access caused by the arbitration of buses by providing plural system buses and preparing plural access routes for master devices and slave devices. CONSTITUTION:System buses 7 and 8 are provided with the same function and controlled by a bus arbiter 1. When there i...

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Bibliographic Details
Main Authors WATARI TAKASHI, KISHI TETSUJI
Format Patent
LanguageEnglish
Published 11.08.1995
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To reduce the loss time of access caused by the arbitration of buses by providing plural system buses and preparing plural access routes for master devices and slave devices. CONSTITUTION:System buses 7 and 8 are provided with the same function and controlled by a bus arbiter 1. When there is a bus request from a certain master device 2, namely, when an access request to a slave device 5 is outputted, the bus arbiter 1 investigates the conditions of the plural system buses 7 and 8 and searches the non-used system bus and when there is such a system bus, the use right of that system bus is applied to the master device 2 that outputs this bus request. When such a system bus does not exist, it is reported to the master device 2, which outputs this bus request, that all the buses can not be used and that master device 2 continuously outputs the bus request to the bus arbiter 1 and is turned to a wait state while disabling access to the slave device 5 until the system buses can be used.
Bibliography:Application Number: JP19940001139