FAST DECIMAL MULTIPLIER

PURPOSE:To simplify a digit multiplier and an adding circuit and decrease the total circuit scale by dividing the respective digits of a multiplier into an even number plus one and multiplying them, and substituting the even number plus one for an odd number even at the time of the addition of the r...

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Bibliographic Details
Main Author NAGATA TOSHIMITSU
Format Patent
LanguageEnglish
Published 23.06.1995
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To simplify a digit multiplier and an adding circuit and decrease the total circuit scale by dividing the respective digits of a multiplier into an even number plus one and multiplying them, and substituting the even number plus one for an odd number even at the time of the addition of the results CONSTITUTION:A multiplicand even-numbering circuit 12 and a multiplicand 1-substituting circuit 11, and a multiplier evennumbering circuit 22 and a multiplier 1-substituting circuit 21 takeout the respective digits of a multiplicand register and a multiplier register separately as the high order three bits and low-order one bit. The high-order digits R are separated by a high-order digit even-numbering circuit 32 and a high-order digit 1-substituting circuit 31 separate four bits of respective digits into the high-order three bits and low-order one bit. And, a tournament type digit even-number adder which adds pairs of S and R' of the same digits is constituted. A main selecting circuit 42 inputs the low-order digits S of a digit even-number multiplier array 3 and the output R' of the high-order digit even-numbering circuit 32 to a digit even-number adder tree 4 in the 1st cycle of arithmetic and inputs the output of the multiplicand even-numbering circuit 12 and 0 in the 2nd cycle.
Bibliography:Application Number: JP19930302107