PLL CIRCUIT AND FAULT DETECTION METHOD FOR PLL CIRCUIT

PURPOSE:To prevent a demodulation error data at the time of data demodulation by detecting a PLL lock state in an abnormal phase difference steady-state with respect to a PLL (phase locked loop) circuit and the fault detection method of the PLL circuit. CONSTITUTION:The PLL circuit having a monostab...

Full description

Saved in:
Bibliographic Details
Main Author SAITO KINYA
Format Patent
LanguageEnglish
Published 18.03.1994
Edition5
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:PURPOSE:To prevent a demodulation error data at the time of data demodulation by detecting a PLL lock state in an abnormal phase difference steady-state with respect to a PLL (phase locked loop) circuit and the fault detection method of the PLL circuit. CONSTITUTION:The PLL circuit having a monostable multivibrator 12 converting a signal shot (SS) pulse with a prescribed width from a peak pulse, a voltage controlled oscillator (VCO) 13 and a phase detection circuit 14 comparing the phase of the SS pulse and the phase of a VCO clock and controlling the VCO 13 based on a control voltage by its phase difference is provided with a pulse width fault detection circuit 20 receiving the SS pulse and the VCO clock to detect a fault state of the PLL according to the error in the pulse width. The circuit 20 converts the pulse width of both pulses respectively into currents Ia, Ib, a capacitor C converts a current difference (Ia-Ib) into a voltage V, and it is compared with reference voltages (VH, VL) to detect a fault state of the PLL.
Bibliography:Application Number: JP19920228559