SYSTEM BUS CONTROL SYSTEM

PURPOSE:To guarantee the data identity between a store-in control system cache memory and a main memory while maintaining the compatibility of the system bus interface of a system input/output control circuit by performing data transfer by using a cache bus when data are expelled from a microprocess...

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Bibliographic Details
Main Author NAGAO HIROKI
Format Patent
LanguageEnglish
Published 04.03.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To guarantee the data identity between a store-in control system cache memory and a main memory while maintaining the compatibility of the system bus interface of a system input/output control circuit by performing data transfer by using a cache bus when data are expelled from a microprocessor to the cache memory. CONSTITUTION:In an information processing system wherein the microprocessor 1 in which the store-in control system cache memory 2 is incorporated, various system input/output circuits, and a main memory 3 are connected by a system bus 5, the cache bus 4 is newly added between the microprocessor 1 and main memory 3 and when the data are expelled from the microprocessor 1 to the cache memory 2, the data transfer is performed by using the cache bus 4. In this constitution, the cache bus 4 is added, so the system bus operation protocol need not be changed and the need to newly develop a system bus connection device is eliminated.
Bibliography:Application Number: JP19920209877