SERIAL DATA COMMUNICATION CONTROLLER

PURPOSE:To extremely easily inform a CPU of that operation clock stop setting becomes invalid during communication. CONSTITUTION:Data to be transmitted to a communication equipment 2 are previously written in a transmitting data buffer and in a normal operating state, however, a communication state...

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Bibliographic Details
Main Author NISHIGUCHI YUKIHIRO
Format Patent
LanguageEnglish
Published 25.02.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To extremely easily inform a CPU of that operation clock stop setting becomes invalid during communication. CONSTITUTION:Data to be transmitted to a communication equipment 2 are previously written in a transmitting data buffer and in a normal operating state, however, a communication state signal 103 to be outputted from the communication equipment 2 is outputted at a '1' level and inputted to a clock controller 3 in the state of performing transmission/reception at the communication equipment 2 and in the case of remaining the transmitting data in the transmitting data buffer. In the case of inputting this communication state signal 103 at the '1' level to the clock controller 3 and setting the stop of an operation clock 101 from a CPU 1, an interruption request signal 102 inputted from the clock controller 3 to the CPU 1 is outputted at the '1' level and at the CPU 1, it is detected that the operation clock stop setting becomes invalid.
Bibliography:Application Number: JP19920206369