DYNAMIC RAM

PURPOSE:To obtain a dynamic RAM wherein it outputs latched data at a data latch circuit when a memory cell is active, it eliminates a dummy operation between a readout operation and a write operation when a pipeline mode which latches stored data in the data latch circuit is executed when the memory...

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Bibliographic Details
Main Author ICHIGUCHI TETSUICHIRO
Format Patent
LanguageEnglish
Published 14.01.1994
Edition5
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To obtain a dynamic RAM wherein it outputs latched data at a data latch circuit when a memory cell is active, it eliminates a dummy operation between a readout operation and a write operation when a pipeline mode which latches stored data in the data latch circuit is executed when the memory cell is on standby and it executes the pipeline mode with good efficiency in direct conjunction with the readout operation and the write operation. CONSTITUTION:The title RAM is provided with the following: a data latch circuit which latches data stored in a memory cell; and an output buffer which outputs the latched data to the outside. When the memory cell 1 is on standby, data (n) in the memory cell 1 is latched in the data latch circuit 7; a transfer- gate transistor 10 between the data latch circuit 7 and the output buffer 8 is turned on; the data (n), at the memory cell 1, which is stored in the data latch circuit 7 is output to the outside via the output buffer 8.
Bibliography:Application Number: JP19920165970