SEMICONDUCTOR MEMORY

PURPOSE:To increase speed of outputting operation by controlling P/S circuits of each memory bank and selecting normal or reserve output. CONSTITUTION:When a defective column address 109 is inputted from an address buffer 104, the defective column address is detected in an address comparator circuit...

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Bibliographic Details
Main Authors KIKUKAWA HIROHITO, SAWADA AKIHIRO
Format Patent
LanguageEnglish
Published 10.02.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To increase speed of outputting operation by controlling P/S circuits of each memory bank and selecting normal or reserve output. CONSTITUTION:When a defective column address 109 is inputted from an address buffer 104, the defective column address is detected in an address comparator circuit 207, a reserve column activation signal 110 and a normal column non-activation signal 211b are generated, and inputted in a reserve column selecting circuit in each memory bank and P/S circuits of each memory bank. A normal memory bank selecting signal 212a generated in a memory bank selecting circuit 208 activates the P/S circuit and a S/P circuit of the normal memory bank. When the column address 109 is the defective column address, a reserve column is selected by a signal 110 in a reserve memory bank. Data of the selected normal memory bank and the reserve memory bank are transferred to the P/S circuit of each bank via a local output line 113. Therefore, the circuit is relieved by using the reserve line and outputting operation can be performed at high speed.
Bibliography:Application Number: JP19920187762