SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To reduce a delay time in a wiring in a chip in a semiconductor integrated circuit. CONSTITUTION:A memory cell array in the semiconductor integrated circuit is divided into plural pieces of blocks, and an output buffer circuit 140 and an output pad 150 for outputting the data in the memory c...

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Bibliographic Details
Main Authors IWAMURA MASAHIRO, YAMAUCHI TATSUMI
Format Patent
LanguageEnglish
Published 22.09.1994
Edition5
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To reduce a delay time in a wiring in a chip in a semiconductor integrated circuit. CONSTITUTION:A memory cell array in the semiconductor integrated circuit is divided into plural pieces of blocks, and an output buffer circuit 140 and an output pad 150 for outputting the data in the memory cell array 120 in the block are provided on every block independently. Further, the semiconductor integrated circuit is provided with a decoding means decoding an address signal so as to read the data of one bit from every memory cell 120 in plural divided blocks. Further, the circuit is provided with an input buffer circuit 520 and input pads 540-541 for inputting a signal and a decoder circuit 530 decoding an address signal on every block independently. Thus, the delay time, etc., from the memory block to the output circuit are reduced.
Bibliography:Application Number: JP19930055528