SEQUENTIAL DATA TRANSFER-TYPE MEMORY AND COMPUTER SYSTEM USING THE SAME

PURPOSE:To provide the memory of a sequential data transfer-type, which can read/write data at one clock cycle, and a computer system whose performance can be made high through the use of the memory. CONSTITUTION:The memory is divided into plural partial memories 10-13. The partial memories are conn...

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Bibliographic Details
Main Authors KOKUNI SATORU, KAMATA EIKI
Format Patent
LanguageEnglish
Published 22.09.1994
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To provide the memory of a sequential data transfer-type, which can read/write data at one clock cycle, and a computer system whose performance can be made high through the use of the memory. CONSTITUTION:The memory is divided into plural partial memories 10-13. The partial memories are connected via a transfer route including registers 34-37, 44-47 and 54-57 arranged at one clock cycle (one cycle time pitch). Data transmitted from a processor to the respective partial memories and data transmitted from the respective partial memories to the processor are sequentially transferred at every one cycle time pitch, and data is read/written in parallel. The memory of the sequential data transfer-type, which can securely read/write data even if the scale of a memory chip becomes large and a machine cycle is shortened, can be realized. Furthermore, the performance of the computer system can be made high by using such memory.
Bibliography:Application Number: JP19930052601