TESTING SYSTEM FOR LSI

PURPOSE:To reduce number of operating test patterns of an LSI and a time to be consumed for testing one LSI by deleting number of the patterns to be used for a scan path test mode. CONSTITUTION:When a switching signal to a scan path test mode is input to an external input pin 1, F/Fs 11.1-11.n disco...

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Bibliographic Details
Main Author KATSUKI KENICHI
Format Patent
LanguageEnglish
Published 08.07.1994
Edition5
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:PURPOSE:To reduce number of operating test patterns of an LSI and a time to be consumed for testing one LSI by deleting number of the patterns to be used for a scan path test mode. CONSTITUTION:When a switching signal to a scan path test mode is input to an external input pin 1, F/Fs 11.1-11.n disconnect from combination circuits 8, 9, 10 to become one large shift register. A phase inverter 6 outputs an inversion signal of an input signal SCK of an external input pin 4 as an output signal SCKN of a clock phase inverter 6, and supplies it as a clock signal of the F/F via a signal line distribution line 7. In this case, when a test signal is input to an external input pin 2, the F/F 11.1 holds the test signal at a rise of the signal SCK and outputs it. Then, the F/F 11.2 holds the output signal of the F/F 11.1 at a rise of next signal SCKN, and outputs it. Thus, the test signal is shifted to the external output pin 3 at the rises of the signals SCK and SCKN.
Bibliography:Application Number: JP19920335894