LAYOUT PATTERN GENERATING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To keep a design rule regarding the layout of elements even with any circuit diagram information by dividing a size of a layout cell by number of lattices for constituting a circuit symbol, and replacing a maximum value of them with a layout cell corresponding to the symbol by setting an int...

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Bibliographic Details
Main Author ITOU MAKIKO
Format Patent
LanguageEnglish
Published 24.06.1994
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PURPOSE:To keep a design rule regarding the layout of elements even with any circuit diagram information by dividing a size of a layout cell by number of lattices for constituting a circuit symbol, and replacing a maximum value of them with a layout cell corresponding to the symbol by setting an interval of the layout cell lattices. CONSTITUTION:A disposing position of a layout pattern element of a semiconductor integrated circuit and a route of wiring are decided by dividing lengths of layout cells 8 corresponding to the symbol of a circuit diagram in X and Y directions by the number of lattices of corresponding circuit diagram symbol 6, selecting the maximum value of them, and setting it as an interval of unit lattices of the layout. The wirings from a terminal of the element to a branch point are deleted from circuit diagram information, and the symbol of the circuit diagram is replaced with the corresponding layout. In this case, the interval of the lattices for deciding the size of the symbol is set to the interval of the unit lattices. The deleted wirings is again wired. Thus, in the case of deciding the wiring, a relative disposing relationship of the elements of the circuit diagram can be considered.
Bibliography:Application Number: JP19920325125