MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• Main Author: OGUCHI YASUHIRO
• Format: Patent
• Language: English
• Published: 21.01.1994
• Edition: 5
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE:To reduce the number of transistors employed and constitute a large- scale exclusive circuit for reading with a few number of transistors by a method wherein the number of bits, constituted by a reading exclusive memory circuit or 4-bit data pattern groups, which are constitutable, are selected and read out. CONSTITUTION:A transistor 101, put on when a word line 108 is selected, supplies the potential of VDD to one diffusion area and connects the other diffusion area to the transistor row selecting wire 119 of N-channel transistor row, which constitutes the data of (0, 0, 0, 0). Another transistor 102, put on when another word line 109 is selected, supplies the potential of VSS to one diffusion area and connects the other diffusion area to the transistor row selecting wire 120 of a P-channel transistor row, which constitutes the data of (1, 0, 0, 0). By this method, necessary data can be read out with the number of transistors, which is fewer than the same so far.