DEMODULATOR

PURPOSE:To make a correct demodulation possible even though a phase deviation occurs in PLL circuit clock pulses by latching pulse train signals with a second clock pulse which consists of an integer multiple frequency and then relatching with a first clock pulse. CONSTITUTION:A PLL circuit generate...

Full description

Saved in:
Bibliographic Details
Main Author SAITO KINYA
Format Patent
LanguageEnglish
Published 13.05.1994
Edition5
Subjects
INFORMATION STORAGE
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:PURPOSE:To make a correct demodulation possible even though a phase deviation occurs in PLL circuit clock pulses by latching pulse train signals with a second clock pulse which consists of an integer multiple frequency and then relatching with a first clock pulse. CONSTITUTION:A PLL circuit generates first PLL clocks (f) which are phase synchronized to peak pulses from a peak detecting circuit and second PLL clocks (e) which have a frequency that is twice the frequency of the clocks (f) and transmits them to a demodulating circuit. At the demodulating circuit, ampsenses A and B are latched by the clocks (e) at a JK-FF 202 and the latched output signals (g) are relatched by the clocks (f) at later stages D-FF 214 and 203. Thus, a correct latch is accomplished by small period clocks (e) even though a small amount of phase deviation occurs in the clocks (f).
Bibliography:Application Number: JP19920282837