FRAME SYNCHRONIZATION CIRCUIT

• Main Author: KUBO NAOTO
• Format: Patent
• Language: English
• Published: 22.04.1994
• Edition: 5
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To smooth a spectrum of a modulator by coding an input signal at a sender side, converting a reception signal into n-sets of signal series at a receiver side so as to add a scramble pattern thereby enhancing the random performance of the signal. CONSTITUTION:A coding circuit 1 at a sender side applies error correction coding to an input signal and an interleave circuit 2 applies interleave conversion to bits by N blocks of a signal subject to block coding from the coding circuit 1. Then a scramble circuit 3 adds a scramble pattern of the same period as an interleave frame to a signal after interleave conversion and sends the result to a radio channel. The sent reception signal is inputted to a receiver side (1-N) conversion circuit 4 and a descramble circuit 9, in which the reception signal is converted into N-series of signals based on a timing signal from a timing signal generating circuit 8. A syndrome pattern correction circuit 6 corrects the signal to eliminate the effect of the scramble pattern and outputs the result.