PRPARATION METHOD FOR DELAY TEST PATTERN

PURPOSE:To establish a pattern preparation method with high processing effi ciency for a theoretical circuit which has a number of internal circuits for the number of inputs by preparing a random input pattern to detect a delay trouble using simulation. CONSTITUTION:An initial value is applied to an...

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Bibliographic Details
Main Authors HIKONE KAZUFUMI, HATAKEYAMA KAZUMI, HAYASHI TERUMINE, IKEDA KOJI
Format Patent
LanguageEnglish
Published 23.03.1993
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PULSE TECHNIQUE
TESTING
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Summary:PURPOSE:To establish a pattern preparation method with high processing effi ciency for a theoretical circuit which has a number of internal circuits for the number of inputs by preparing a random input pattern to detect a delay trouble using simulation. CONSTITUTION:An initial value is applied to an FF 51 and an external input pin 52 to perform a simulation of a pre-stage combination circuit 53. Then, a transition signal of the FF 51 is determined using simulation results. An initial value of an FF 54 not presented in the FF 51. An initial value of an external input pin 55 not presented in the external input pin 52 and a transition value are determined. Here, a signal to be applied is determined so that more change signals appear, which provides a higher detection rate as compared with that when it is determined so that less change signals do. Then, a delay trouble simulation of a combination circuit 56 is performed using the initial value and the transition value of the external input pin 55 and the FF54 thereby removing troubles detected from a trouble list.
Bibliography:Application Number: JP19910237808