SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type MOSFET and providing a proper load means thereon. CONSTITUTION:An address buffer ADBO is supplied to a base of a differential transistor T2 thr...
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Format | Patent |
Language | English |
Published |
19.03.1993
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Subjects | |
Online Access | Get full text |
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Abstract | PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type MOSFET and providing a proper load means thereon. CONSTITUTION:An address buffer ADBO is supplied to a base of a differential transistor T2 through an emitter follower circuit. Collector output of the differential transistor T2 constituting ECL is inputted to a next predecording circuit as a signal of an ECL level]. as it is. At this time, only three predecoding circuits forming a selective signal at a high level of 24 kinds of predecoding circuits by a combination of predecoding circuits pass a direct current while no direct current path is formed in the rest of 21 wired OR circuits so that power consumption can be sharply reduced. |
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AbstractList | PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type MOSFET and providing a proper load means thereon. CONSTITUTION:An address buffer ADBO is supplied to a base of a differential transistor T2 through an emitter follower circuit. Collector output of the differential transistor T2 constituting ECL is inputted to a next predecording circuit as a signal of an ECL level]. as it is. At this time, only three predecoding circuits forming a selective signal at a high level of 24 kinds of predecoding circuits by a combination of predecoding circuits pass a direct current while no direct current path is formed in the rest of 21 wired OR circuits so that power consumption can be sharply reduced. |
Author | NAKAI NOBUAKI |
Author_xml | – fullname: NAKAI NOBUAKI |
BookMark | eNrjYmDJy89L5WRQD3b19XT293MJdQ7xD1Lw9AtxdQ9yDHF1UXD2DHIO9QxRcHEN83R25WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BHgamZubmJqaOxkQoAQCgkCWZ |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | JPH0567745A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JPH0567745A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 14:46:31 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JPH0567745A3 |
Notes | Application Number: JP19910257032 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930319&DB=EPODOC&CC=JP&NR=H0567745A |
ParticipantIDs | epo_espacenet_JPH0567745A |
PublicationCentury | 1900 |
PublicationDate | 19930319 |
PublicationDateYYYYMMDD | 1993-03-19 |
PublicationDate_xml | – month: 03 year: 1993 text: 19930319 day: 19 |
PublicationDecade | 1990 |
PublicationYear | 1993 |
RelatedCompanies | HITACHI LTD |
RelatedCompanies_xml | – name: HITACHI LTD |
Score | 2.4276319 |
Snippet | PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930319&DB=EPODOC&locale=&CC=JP&NR=H0567745A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFH_MKepNp-L8ogepp-Jmvw9FtrS1LawttR27jTRLYZc5XMV_35faTS96Cwm8JA_eZ97vBeCeDS2DMtNUuDGoFE21qGIznSqM2Rw94MqwmUjoT2IjKLRops86sNxiYZo-oZ9Nc0SUKIbyXjf6ev2TxHKb2srNY7nEqbdnP3dcedHCxVQBypHdseOliZsQmRAnSuU4cwI09Ojp6KM92BdetGiz703HApSy_m1R_BM4SJHYqj6FDl_14IhsP17rweGkfe_GYSt6mzN4eBUcS2K3IHmSSaKV7Us2Qr0jkTAjRZhLrjcNiXcOku_lJFBwx_nudvMo3Z1NvYAuBv38EqQnjFt0VSur0hxoJbWpJZ4wS-TlYmhxavSh_yeZq3_WruH4u2RPVYb2DXTr9w9-i2a1Lu8ahnwBYRp4qg |
link.rule.ids | 230,309,786,891,25594,76904 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8JAEJ4gGvGmqBGfPZh6aqT0fWgMbFvbCm1TC-FGtktJuCCRGv--s7WgF71tdpPZ3UnmufPNAtwz2dQpMwyp0LsLSVVMKllMoxJjVoEe8EK3GE_ojyLdH6vhVJs2YLnFwlR9Qj-r5ogoUQzlvaz09fonieVUtZWbx3yJU29PXmY74ryGiykclCM6A9tNYicmIiF2mIhRavto6NHT0fp7sG9gRMjb7LuTAQelrH9bFO8YDhIktipPoFGs2tAi24_X2nA4qt-7cViL3uYUHl45x-LIGZMsTgXeyvY57aPeEUiQknGQCY47CYh7BoLnZsSXcMfZ7nazMNmdTTmHJgb9xQUIPYxbNEXNF7nRVXNqUZM_YebIy7lsFlTvQOdPMpf_rN1By89Gw9kwiF6u4Oi7fE-RZOsamuX7R3GDJrbMbyvmfAEqiHuV |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SEMICONDUCTOR+INTEGRATED+CIRCUIT+DEVICE&rft.inventor=NAKAI+NOBUAKI&rft.date=1993-03-19&rft.externalDBID=A&rft.externalDocID=JPH0567745A |