SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type MOSFET and providing a proper load means thereon. CONSTITUTION:An address buffer ADBO is supplied to a base of a differential transistor T2 thr...

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Bibliographic Details
Main Author NAKAI NOBUAKI
Format Patent
LanguageEnglish
Published 19.03.1993
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE:To reduce power consumption of a decoding circuit decoding an ECL signal by receiving a plurality of ECL output signals by means of a F-channel type MOSFET and providing a proper load means thereon. CONSTITUTION:An address buffer ADBO is supplied to a base of a differential transistor T2 through an emitter follower circuit. Collector output of the differential transistor T2 constituting ECL is inputted to a next predecording circuit as a signal of an ECL level]. as it is. At this time, only three predecoding circuits forming a selective signal at a high level of 24 kinds of predecoding circuits by a combination of predecoding circuits pass a direct current while no direct current path is formed in the rest of 21 wired OR circuits so that power consumption can be sharply reduced.
Bibliography:Application Number: JP19910257032