PLL CIRCUIT

PURPOSE:To obtain a clock with less jitter in oscillation frequency by selecting the maximum or minimum oscillation frequency at the time of switching a selector circuit 4 and switching the output voltage of a loop filter when it returns within the control range. CONSTITUTION:For example, when frequ...

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Bibliographic Details
Main Author MINAMI KOJI
Format Patent
LanguageEnglish
Published 19.02.1993
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
SEALS
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Summary:PURPOSE:To obtain a clock with less jitter in oscillation frequency by selecting the maximum or minimum oscillation frequency at the time of switching a selector circuit 4 and switching the output voltage of a loop filter when it returns within the control range. CONSTITUTION:For example, when frequency fR of a reference signal where a selector circuit 10 selects a signal (a) is higher than 30kHz, a loop filter 3 controls the input voltage to increase. When a comparator circuit 11 detects an operation point exceeds P5 that is, it exceeds V5, the selector circuit 10 once selects a signal (b) with the highest oscillation frequency among signals (a) to (c). When the comparator circuit 11 detects the operation point is returned to pass the P5, the selector circuit 10 is switched to select a signal (b). Thus, the voltage addition circuit or the like to pull in the output voltage of the loop filter 3 within the control range forcedly is unnecessitated, resulting in less noise.
Bibliography:Application Number: JP19910197678