MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To efficiently arrange an input terminal on a gate array semiconductor substrate by placing the arranging area of the input/output terminal to be on the outside of the arranging area of the input/output basic cell and providing a wiring area between the arranging area of the input/output ter...

Full description

Saved in:
Bibliographic Details
Main Author OGUCHI YASUHIRO
Format Patent
LanguageEnglish
Published 12.02.1993
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:PURPOSE:To efficiently arrange an input terminal on a gate array semiconductor substrate by placing the arranging area of the input/output terminal to be on the outside of the arranging area of the input/output basic cell and providing a wiring area between the arranging area of the input/output terminal and the arranging area of the input/output basic cell. CONSTITUTION:A wiring area 106, which sets metal wiring that connects an input/output basic cell 105, is arranged between an input terminal arranging area 103 constituted of an input terminal 104 and the arranging area of an input/output basic cell 105. Since the input/output terminal 104 is connected with the input/output basic cell 105 by the metal wiring, the arranging positions are not specified. Therefore, the input/output terminal 104 is set at the discretionary position in the input/output terminal arranging area 103. Thus, the input/ output terminal 104 is arranged at the corner of a semiconductor substrate without increasing a cell library by a master slice type gate array.
Bibliography:Application Number: JP19910192960