JPH05290570

PURPOSE:To decrease the number of a logic stage without damaging the start potential of a word line and to accelerate access by making memory arrays un-accessed simultaneously a pair, switching them with a switching M0STr and driving each memory array. CONSTITUTION:This memory is provided with the m...

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Bibliographic Details
Main Authors OTA TATSUYUKI, MAEDA TOSHIO
Format Patent
LanguageEnglish
Published 05.11.1993
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PURPOSE:To decrease the number of a logic stage without damaging the start potential of a word line and to accelerate access by making memory arrays un-accessed simultaneously a pair, switching them with a switching M0STr and driving each memory array. CONSTITUTION:This memory is provided with the memory arrays ARY0 and ARY1, ARY2 and ARY3 as two pairs of the memory arrays, and a chip area is reduced by switching them by switchs SHR0 and SHR1 and sharing a sense amplifier S.A and an input/output bus I/O. When the word line of the memory array ARY0 is selected, the output of an X address buffer XAB is inputted to an X decoder XDEC directly through a predecoder Pre.DEC. Thus, access is accelerated by the difference of the number of the logic stage for raising no defective word line. Further, when the defective word line 3 is selected in the array ARY0, the word line 6 of the redundant area 2 of the array ARY1 is selected by the output of a redundancy relief circuit 1 and the switch SHR0 is turned off and the SHR1 is turned on.
Bibliography:Application Number: JP19920092591