JPH05242697

PURPOSE:To reduce the circuit scale of a semiconductor memory device and to improve the yield of chips for the storage device, which has a plural word configuration, by commonly using one test signal generating circuit. CONSTITUTION:Test control signals 107 outputted by a test signal generating circ...

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Bibliographic Details
Main Author SHINDO TAKESHI
Format Patent
LanguageEnglish
Published 21.09.1993
Edition5
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To reduce the circuit scale of a semiconductor memory device and to improve the yield of chips for the storage device, which has a plural word configuration, by commonly using one test signal generating circuit. CONSTITUTION:Test control signals 107 outputted by a test signal generating circuit 8 are initially set so as to perform writing operations to a RAM 7. Moreover, test address signals 106 outputted from the circuit 8 count from an address zero up to higher addresses one at a time. When the address value of the signals 106 becomes equal to the value of array output signals 105, writings to all addresses are ceased and the signals 106 are set to a zero address. Furthermore, in the read sequence which follows, the sequence is automatically advanced one similar to the write sequence. Moreover, in the case of the RAM, which has a plural word configuration, testing of all RAMs is done through the use of one built-in test circuit by inputting each of the RAM signals 105, which are switched by selectors, to the circuit 8.
Bibliography:Application Number: JP19920042640