JPH05235044

• Main Author: KONO YASUTAKA
• Format: Patent
• Language: English
• Published: 10.09.1993
• Edition: 5
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To manufacture the title field effect transistor having high performances such as high breakdown voltage and low source resistance by a method wherein the distance between the implanted isolation interface and the isolation interface connecting the contact of a gate electrode to a drain electrode end is increased without changing the distance between a gate electrode and source.drain electrode. CONSTITUTION:An isolation layer 4 is to be formed by a method wherein the part to form the title field effect transistor of n-GaAs layers 5 formed on a substrate is ion implanted with boron using a patterned photoresist as a mask so as to widen the space of the n-GaAs layers 5 between source.drain electrodes 2 and a gate electrode 1 to be formed later. Through these procedures, a linear isolation interface can be formed to widen the space of n-GaAs layers 5 so that the distance from the contact 13 between the gate electrode 1 and the implanted isolation interface to a drain electrode end A may be increased to relieve the maximum field impressed on the implanted isolation layer 4.