BIT SYNCHRONIZATION SYSTEM AND BURST DEMODULATOR

PURPOSE:To attain high speed bit synchronization by detecting a change in a phase of a pi/2 shift BPSK or a pi/4 shift QPSK preamble and to realize stable burst demodulation with a shorter preamble through inverse modulation pattern synchronization. CONSTITUTION:A phase change detection means 3 extr...

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Bibliographic Details
Main Author YOSHIDA NAOMASA
Format Patent
LanguageEnglish
Published 20.08.1993
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PURPOSE:To attain high speed bit synchronization by detecting a change in a phase of a pi/2 shift BPSK or a pi/4 shift QPSK preamble and to realize stable burst demodulation with a shorter preamble through inverse modulation pattern synchronization. CONSTITUTION:A phase change detection means 3 extracts a 1/2 bit frequency component by using an alternate data modulation preamble of a pi/2 shift BPSK or a pi/4 shift QPSK. A multiplier means 5 takes correlation with a reference signal and averages the result, and an inverse tangent calculation means 7 obtains a bit timing. A signal point is sampled or interpolated by a value doubling an output of the inverse tangent calculation means 7. Moreover, an output of the inverse tangent calculation means 7 is used, an inverse modulation pattern synchronization means 10 extracts synchronization information of an inverse modulation pattern and the preamble is inversely modulated by using the synchronization pattern. Carrier recovery and phase demodulation are implemented by using a non-modulation signal subject to inverse modulation.
Bibliography:Application Number: JP19910342782