SYSTEM BUS INTERFACE CIRCUIT

PURPOSE:To keep the fault processing range to an irreducible minimum at the time of the fault occurrence by erasing only the data stored in a transmission buffer when a monitoring timer overflows. CONSTITUTION:A bus protocol monitoring circuit 10 detect a command from a local bus 3 and starts a time...

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Bibliographic Details
Main Authors OKADA KATSUYUKI, KOMACHIYA TADAYOSHI, SHIBATA YUJI, ASAI MASAO, OKAZAKI MAKOTO
Format Patent
LanguageEnglish
Published 06.08.1993
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To keep the fault processing range to an irreducible minimum at the time of the fault occurrence by erasing only the data stored in a transmission buffer when a monitoring timer overflows. CONSTITUTION:A bus protocol monitoring circuit 10 detect a command from a local bus 3 and starts a timer 11. In case no answer comes for this command for more than the constant time, the timer 11 overflows. A clear circuit 12 detects the overflow and outputs a clear signal. The clear signal is inputted to a reception control circuit 6, suppresses the reception of the command to prevent a new command from being written in a transmission buffer 4. A clear signal is supplied to a transmission control circuit 7, erasing the data in the transmission buffer 4 by counting up the output address counter to match the input address and the output address. Thus, the data in a reception buffer 5 can be used as it is at the fault recovering of the system.
Bibliography:Application Number: JP19920007794