MULTIPLE TIMER CIRCUIT

PURPOSE:To form the timer circuit with a comparatively small circuit scale even when number of channels (n) is large by devising the timer to be in operation independently of each channel. CONSTITUTION:A timer counter 11 outputs a count in an m-bit binary number. A multiple address counter 12 output...

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Bibliographic Details
Main Author KONO OSAMU
Format Patent
LanguageEnglish
Published 01.12.1992
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
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Summary:PURPOSE:To form the timer circuit with a comparatively small circuit scale even when number of channels (n) is large by devising the timer to be in operation independently of each channel. CONSTITUTION:A timer counter 11 outputs a count in an m-bit binary number. A multiple address counter 12 outputs an n-bit address. A RAM 14 stores an m-bit count final value 108 in m-bit, a 1-bit ROM output timer signal 107 and a trigger signal 106 based on the address and outputs the result. A ROM 13 receives a trigger input signal 101 representing the start of the timer, a count 102, a RAM output count final value, and a RAM output timer signal 104 and outputs a multiplex timer signal representing the conversion of the input trigger signal 103 to a terminal 109.
Bibliography:Application Number: JP19910116392