SEQUENCE OPERATION PROCESSING DEVICE

PURPOSE:To obtain the sequence operation processing device unnecessitating the reset of a sequence operation valid/invalid flag and unnecessitating a dummy instruction or the like even when there is an instruction equal to a sequence operation instruction as one part of an instruction with the form...

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Bibliographic Details
Main Author NAKAGAWA TERUO
Format Patent
LanguageEnglish
Published 25.09.1992
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To obtain the sequence operation processing device unnecessitating the reset of a sequence operation valid/invalid flag and unnecessitating a dummy instruction or the like even when there is an instruction equal to a sequence operation instruction as one part of an instruction with the form of a data in the numerical operation instruction of addition, subtraction, multiplication and division or the like. CONSTITUTION:An address area judging means 102 and a sub routine instruction judging means 107 are provided, the checks of the sequence operation instruction and a sub routine instruction and the execution of the sequence operation instruction are executed only in the range of a set address area and since the control of an instruction cache is automatically executed so as to unnecessitate the setting of the sequence operation valid/invalid flag, the sequence operation processing device can be obtained while simplifying the preparation of a program, reducing a memory and shortening processing time.
Bibliography:Application Number: JP19910015376