DIGITAL MULTIPLEXER

PURPOSE:To improve the transmission efficiency at data transmission by generating a multiplexed flag pattern for frame synchronization from a flag pattern of a transmission data of each channel. CONSTITUTION:HDLC data parts 6a-6c of a transmission data inputted from each of channels 1a-1c at a sende...

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Bibliographic Details
Main Author FUJIO HIROYUKI
Format Patent
LanguageEnglish
Published 14.09.1992
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Summary:PURPOSE:To improve the transmission efficiency at data transmission by generating a multiplexed flag pattern for frame synchronization from a flag pattern of a transmission data of each channel. CONSTITUTION:HDLC data parts 6a-6c of a transmission data inputted from each of channels 1a-1c at a sender side are subject to time division multiplex at a multiplexer circuit 2a. In this case, flag patterns 7a-7c of each transmission data are subject to time division multiplex for each bit by the multiplexer circuit 2a. An HDLC flag pattern generated in this way is outputted as a multiplexed flag pattern 9 of a multiplexed frame 8.
Bibliography:Application Number: JP19910038864