COUNTER

PURPOSE:To speed up the counter. CONSTITUTION:When a logic '0' signal of a data processing signal TSK is inputted to an OR circuit 18, a logic inversion output Q0- of a flip-flop 14 is outputted from the OR circuit 18, it is applied to a count enable input terminal CE of a flip-flop 15, an...

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Bibliographic Details
Main Author TAKEBE SHIN
Format Patent
LanguageEnglish
Published 21.08.1992
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PULSE TECHNIQUE
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PURPOSE:To speed up the counter. CONSTITUTION:When a logic '0' signal of a data processing signal TSK is inputted to an OR circuit 18, a logic inversion output Q0- of a flip-flop 14 is outputted from the OR circuit 18, it is applied to a count enable input terminal CE of a flip-flop 15, and in accordance with it, as for an output Q1 of the flip-flop 15, its logical state is varied at every period of two folds of a period of a clock pulse signal CK. When a logic '1' signal of the data processing signal TSK is inputted to the OR circuit 18, the logic signal is applied to the count enable input terminal CE of the flip-flop 15 from the OR circuit 18, and in accordance with it, as for the output Q1 of the flip-flop 15, its logical state is varied at every same period as the period of the clock pulse signal CK.
Bibliography:Application Number: JP19900408766