LAYOUT METHOD FOR CMOS INTEGRATED CIRCUIT

• Main Authors: KIKUKAWA HIROHITO, YAMADA TOSHIRO
• Format: Patent
• Language: English
• Published: 28.07.1992
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE:To enable the circuit element such as transistor, etc., to be arranged on the whole semiconductor substrate thereby increasing the integration degree by a method wherein the power supply lines and the signal lines are allotted to respective wiring layers of a CMOS integrated circuit. CONSTIT...