LAYOUT METHOD FOR CMOS INTEGRATED CIRCUIT

PURPOSE:To enable the circuit element such as transistor, etc., to be arranged on the whole semiconductor substrate thereby increasing the integration degree by a method wherein the power supply lines and the signal lines are allotted to respective wiring layers of a CMOS integrated circuit. CONSTIT...

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Bibliographic Details
Main Authors KIKUKAWA HIROHITO, YAMADA TOSHIRO
Format Patent
LanguageEnglish
Published 28.07.1992
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PURPOSE:To enable the circuit element such as transistor, etc., to be arranged on the whole semiconductor substrate thereby increasing the integration degree by a method wherein the power supply lines and the signal lines are allotted to respective wiring layers of a CMOS integrated circuit. CONSTITUTION:Within a CMOS integrated circuit, Vss lines 24 and Vcc lines 25b (25a) are provided respectively on the first layer and the second layer to eliminate the wiring regions so that the circuit elements such as transistors, etc., may be arranged on the whole semiconductor substrate thereby enabling the integration degree to be increased Furthermore, the gaps between signal lines can be widened; the wiring length of the signal lines and the power supply lines can be shortened; and the wiring width of the power supply lines can be widened so that the problems such as the mutual interference between the signal lines, the timing skew between signals, the drop in power supply voltage, the floating of reference voltage, etc., may be settled.
Bibliography:Application Number: JP19900338090