SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE:To enable high speed operation without lowering a gain even if channel width becomes narrow by controlling a couple of overlapped MOSFETs with only one gate electrode and making wide an effective channel width. CONSTITUTION:A Si layer 2 is formed thinner at the upper part of a source region...

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Bibliographic Details
Main Authors ARIMOTO YOSHIHIRO, HORIE HIROSHI
Format Patent
LanguageEnglish
Published 25.06.1992
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Summary:PURPOSE:To enable high speed operation without lowering a gain even if channel width becomes narrow by controlling a couple of overlapped MOSFETs with only one gate electrode and making wide an effective channel width. CONSTITUTION:A Si layer 2 is formed thinner at the upper part of a source region 5 in the side of supporting substrate and a gate voltage is applied to a gate electrode 8 to form a perfectly depleted channel region 9 in the side of Si layer and to control a channel region 10 in the side of supporting substrate with a gate electrode 8. Therefore, the effective channel width becomes equal to a sum of the channel region 9 in the side of Si width and the channel region 19 in the side of supporting substrate, making wider the channel width. Accordingly, a gain of MOSFET is not lowered even when the channel width on the one element pattern becomes narrow. A couple of MOSFETs are overlappingly arranged in the vertical direction to form a dual-channel MOSFET to control two channels with only one gate electrode. All channels are controlled with only one gate electrode to improve the gain of MOSFET and further narrower the channel width on the pattern.
Bibliography:Application Number: JP19900308203