INDICATING FAULT POSITION OF LOGIC INTEGRATED CIRCUIT

PURPOSE:To correctly locate a fault position without receiving influence of a hazard, etc., by inserting at least one logic fault in logic data which is inputted into a logic integrated circuit. CONSTITUTION:An output value reflecting a fault intentionally made for every test pattern is recorded in...

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Bibliographic Details
Main Authors IKEDA MASAHARU, KASUGA KAZUO, FUNABIKI TAKAHIRO
Format Patent
LanguageEnglish
Published 21.05.1992
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:PURPOSE:To correctly locate a fault position without receiving influence of a hazard, etc., by inserting at least one logic fault in logic data which is inputted into a logic integrated circuit. CONSTITUTION:An output value reflecting a fault intentionally made for every test pattern is recorded in a test pattern file 2. Thereafter, the comparison process is carried out, which collate the output expected value at the input time of the normal logic data recorded in a test pattern file 1, the output value of fault simulation recorded in the test pattern file 2 and reflecting the fault intentionally set up, and a test result 3 with one another. Further, an inversion part where the output expected value changes and the number of fail pins recorded in the file 3 are compared with each other and the result is output as a comparison result 6. It is accurately specified that the part of the fault F intentionally made is a true fault candidature in the case both agree in the comparison result 6.
Bibliography:Application Number: JP19900274179