METHOD AND APPARATUS FOR PREPARING TEST PATTERN OF LOGICAL CIRCUIT

PURPOSE:To efficiently prepare a test pattern of high quality by allotting a logical value only to a bidirectional edge judged to allot the logical value to determine an input pattern. CONSTITUTION:In the input pattern generating processing to an input edge, an input pattern is generated only in the...

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Bibliographic Details
Main Authors HIKONE KAZUFUMI, HATAKEYAMA KAZUMI, HAYASHI TERUMINE, IKEDA KOJI
Format Patent
LanguageEnglish
Published 11.05.1992
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Summary:PURPOSE:To efficiently prepare a test pattern of high quality by allotting a logical value only to a bidirectional edge judged to allot the logical value to determine an input pattern. CONSTITUTION:In the input pattern generating processing to an input edge, an input pattern is generated only in the input edge other than a bidirectional edge. In a bidirectional edge input pattern allotting judging part 12, by calculating the logical value of each signal line only on the basis of the input pattern generated by an input edge input pattern generating part 11, the logical value of the control signal of the output buffer of each bidirectional edge is calculated and a bidirectional edge wherein the logical value of the control signal is 0 is judged to be possible to allot the input pattern. In a bidirectional edge input pattern generating part 13, the input pattern is allotted only to the bidirectional edge judged to be possible to allot the input pattern by weighting random numbers. By this method, there is effect capable of preparing a test pattern having high trouble detection capacity.
Bibliography:Application Number: JP19900256928