COUNTER TEST METHOD

PURPOSE:To allow the method with the less member of patters for test and not to decrease a maximum operating frequency at the time of testing by controlling a clock, a reset signal and a carry-in signal for each counter for an object to be tested so as to conduct the test. CONSTITUTION:Outputs of a...

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Bibliographic Details
Main Author TSUNEOKA TAKASHI
Format Patent
LanguageEnglish
Published 02.04.1991
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:PURPOSE:To allow the method with the less member of patters for test and not to decrease a maximum operating frequency at the time of testing by controlling a clock, a reset signal and a carry-in signal for each counter for an object to be tested so as to conduct the test. CONSTITUTION:Outputs of a 12-bit counter exist in 4096 ways by permutation of 12 bits, but test is conducted for 4-bit output each of the counter through the division of the counter constitution, then test patters required only 16X3=48 ways. The operating limit frequency fmax of the period counter is expressed in equation I, where Tpd is a propagation delay time of the counter, Tsu is a set up time and Tskew is a skew of the clock. The skew Tskew is suppressed small because of the limited effect only in the wiring coverage length in a gate array, thereby improving the operating limit frequency fmax.
Bibliography:Application Number: JP19890211750