DMA TRANSFER SYSTEM AND SINGLE CHIP PROCESSOR UNIT

PURPOSE:To reduce the hardware of a unit, for which a microprocessor unit (MPU) and a DMA controller are formed to be one chip, by reading transfer information from a memory by a CPU corresponding to a data transfer request and setting the information to the DMA controller. CONSTITUTION:When a chain...

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Bibliographic Details
Main Authors MARUYAMA TAKASHI, YU KEIICHI
Format Patent
LanguageEnglish
Published 18.02.1991
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To reduce the hardware of a unit, for which a microprocessor unit (MPU) and a DMA controller are formed to be one chip, by reading transfer information from a memory by a CPU corresponding to a data transfer request and setting the information to the DMA controller. CONSTITUTION:When a chain request is generated from a DMA controller 3 of a single chip processor unit (PU) 1, an MPU 2 controls an I/O 8 and a memory 9 through a memory management unit (MMO) 4 corresponding to an interruption request 12. Data read from the memory 9 are stored to a built-in chain status register and set to the controller 3. With this configuration not to require the hardware of a data bus system, the single chip processor unit is formed in the shape of a mountain and link array chain operation is easily changed.
Bibliography:Application Number: JP19890169813