JPH033251B

PURPOSE:To easily perform each operation of generation, impression, and observation of test data, by constituting both series of flip flop groups at the master side and the slave side as shift registers equipped with feedback loops. CONSTITUTION:When a trouble occurs in a combined circuit, to which...

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Bibliographic Details
Main Authors TAKAHASHI MASANOBU, FUNATSU SHIGEHIRO
Format Patent
LanguageEnglish
Published 18.01.1991
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:PURPOSE:To easily perform each operation of generation, impression, and observation of test data, by constituting both series of flip flop groups at the master side and the slave side as shift registers equipped with feedback loops. CONSTITUTION:When a trouble occurs in a combined circuit, to which bit patterns are supplied through signal lines 130-1, 130-2, 130-3, and 130-4 and the influence of the trouble appears on the signal line 130-3 of a clock cycle 9, it is successively transmitted to a flip flop group 201 and 208 at the master side. As a result, output bit patterns Q1, Q2, Q3 and Q4 of F/F circuits 201, 203, 205 and 207 at a clock cycle 15 finally become (1, 1, 1 and 0), and the output bit patterns Q1, Q2, Q3 and Q4 are different from those of the F/F circuits 201, 203, 205 and 207 in a normal case.
Bibliography:Application Number: JP19820003784