SCANNING DESIGN CORRESPONDENCE N-STAGE PROTECTING CIRCUIT

PURPOSE:To enable non-scanning design and scanning design by providing two circuits which ANDs (n) positive and negative electrode outputs of FF(flip- flop) circuits which shift input data to following stages in sequence. CONSTITUTION:The data is shifted by the FF circuits 11-1n in order and the pos...

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Bibliographic Details
Main Author KOMORI HIROYUKI
Format Patent
LanguageEnglish
Published 28.11.1991
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:PURPOSE:To enable non-scanning design and scanning design by providing two circuits which ANDs (n) positive and negative electrode outputs of FF(flip- flop) circuits which shift input data to following stages in sequence. CONSTITUTION:The data is shifted by the FF circuits 11-1n in order and the positive electrode outputs and negative electrode outputs are inputted to AND circuits A1 and A2 respectively. The outputs of the circuits A1 and A2 are inputted to a NOR circuit NR1, which outputs 0 when (n) 1-level or 0-level data succeed. The output 0 of this circuit circuit NR1 and a clock signal are inputted to a NOR circuit NR2 to generated a pulse signal which is the inversed clock signal. An (n)-stage protection output can be generated by an FF circuit 20 by input with the pulses. Consequently, this (n)-stage protecting circuit which does not use the SR latch circuit of a scanning design inhibiting circuit can be used in common for both the non-scanning design and scanning design.
Bibliography:Application Number: JP19900067612