LOGIC SIMULATION METHOD

• Main Authors: ONO YASUNOBU, AMANO NOBUTAKA, YAMADA YASUNORI
• Format: Patent
• Language: English
• Published: 27.11.1991
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE:To efficiently execute the correction of logic by enabling logic resimulation from a proper time point without reinputting logic simulation input information from the beginning. CONSTITUTION:Location information is outputted to show the arrangement of respective elements constituting a logic circuit model, which are built in the compiler or linker of the logic circuit model, on a memory and based on this location information, positions storing a logic value on a structure model and a variable value in a function model are recognized in the middle of logic simulation. Then, those values are preserved at arbitrary intervals together with logic simulation execution time information composed of a registered event and a logic simulation execution step. By rearranging the logic value and the variable value on the logic circuit model, the logic simulation is restarted from the time point when preserving the logic value and the variable value. Thus, time for logic simulation can be shortened.