DATA PROCESSOR
PURPOSE:To increase the data processing speed by recognizing easily the end data on a data train attendant to each command. CONSTITUTION:A 1st processor 11 sends the transfer information to a data bus 14 and also sends a specific address signal to the address buses AD2 - AD31 respectively at transfe...
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Main Author | |
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Format | Patent |
Language | English |
Published |
20.11.1991
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE:To increase the data processing speed by recognizing easily the end data on a data train attendant to each command. CONSTITUTION:A 1st processor 11 sends the transfer information to a data bus 14 and also sends a specific address signal to the address buses AD2 - AD31 respectively at transfer of the end data on a data train attendant to each command. A detection neabs 15 generates an end detection signal that shows the detection of the end data. A FIFO memory 13 stores the transfer information and the end detection signal in correspondance to each other. A 2nd processor 12 reads out successively the storage contents of the memory 13 to receive the transfer information. In this case, the processor 12 can know the end data on the data train without counting the number of data since the end detection signal is put in correspondance to the read-out transfer information. Thus the load of a data processor is extremely reduced and the information transfer speed is increased. |
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Bibliography: | Application Number: JP19900059531 |