ASYNCHRONOUS DATA ACCESS SYSTEM FOR RAM

• Main Authors: KAMEDA MASARU, TAKEI KAZUHIRO
• Format: Patent
• Language: English
• Published: 19.11.1991
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To attain transmission reception of sure data by comparing the phase of a readout control signal with the phase of a load timing signal and shifting the phase of the readout control signal by a prescribed phase from a usual location when the signal phases are overlapped. CONSTITUTION:A write control signal WE and a readout control signal OE to/from a RAM 1 are generated by using a reception clock synchronously with a reception data R DATA when write/readout of an asynchronous data to/from the RAM 1 is implemented via an S/P converter 2 and a P/S converter 3, a comparator 8 compares the phase of the readout control signal OE with the phase of a load timing signal P/S LOAD TIM for the P/S converter and a phase shift control section 9 shifts a prescribed bit number from the usual position for the phase of the readout control signal OE when the phases of the signals are overlapped.