BUS COMMUNICATION CONTROL SYSTEM FOR INFORMATION SYSTEM

• Main Authors: OKADA KATSUYUKI, OKAMOTO HISASHI, TANIHIRA HISAMITSU, HIROSE TETSUHIKO
• Format: Patent
• Language: English
• Published: 12.11.1991
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE:To avoid the occurrence of the nonused state of a bus by information a memory device of the full state of a processor or the communication buffer of bus transposition, and executing a retry request when memory write access to the memory device arises from another device in this state. CONSTITUTION:The processor 11 supervises a common bus 14, and fetches the memory write access to the communication buffer, and when the communication buffer turns into the full state, the processor 11 asserts a communication buffer full signal 17. When in this state, the write access arises from an input/ output device (IO) 13n to the memory (CM) 12, since the CM 12 can not receive the access, it informs the IO 13n of the retry request by a receiving status. On the other hand, before the IO 13n acquires timing, the processor 11 sends the contents of the communication buffer to the inside of the processor so as to made room for the communication buffer, and negates the communication buffer full signal 17. Thus, the occurrence of the occurrence of the nonused state of the bus is avoided.