TESTING METHOD FOR SEMICONDUCTOR
PURPOSE:To shorten a standby time by a method wherein an IC is replaced with a separate unmeasured IC when the IC is judged to be inferior with respect to a specific test item and a test is carried out all at once along with the other IC from the next test item and usual replacement is performed aft...
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Main Author | |
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Format | Patent |
Language | English |
Published |
05.08.1991
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE:To shorten a standby time by a method wherein an IC is replaced with a separate unmeasured IC when the IC is judged to be inferior with respect to a specific test item and a test is carried out all at once along with the other IC from the next test item and usual replacement is performed after a round of test items. CONSTITUTION:A tester 1 sends a test start signal to a CPU 5 and writes a test number in a memory device 6 and allows a handler 4 to set an IC to each DUT 3 to test the IC with respect to test items TEST 1 - 5. when the IC of the first DUT1 is judged to be inferior in the TEST 2, the CPU 5 allows the handler 4 to replace the inferior IC with the next IC to set the IC to the DUT1 and writes a test number in the device 6 to start a test along with the unmeasured IC of the other DUT from the next TEST 3. When the IC is a good product, the IC is replaced with the next IC when the test items stored in the device 6 are completed. By this method, the IC can be measured without generating the standby time of test processing in the DUT where the inferiority of the IC is generated. |
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Bibliography: | Application Number: JP19890318122 |