SIGNAL DISCRIMINATING CIRCUIT

• Main Author: SEKO KAZUYUKI
• Format: Patent
• Language: English
• Published: 05.07.1991
• Subjects: ADVERTISING; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION; CRYPTOGRAPHY; DISPLAY; EDUCATION; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PHYSICS; PICTORIAL COMMUNICATION, e.g. TELEVISION; SEALS

PURPOSE:To improve the frequency discrimination accuracy of a synchronizing input signal by counting stabilized clock pulses by a counter timer and generating a reference pulse for comparison, then making comparison as to whether the synchronization of the input signal is shorter than the time of the reference pulse or not. CONSTITUTION:A frequency dividing circuit CT is reset by a reset signal generating circuit 2 which differentiates the input synchronizing signal via a delay circuit 1 and the clock pulses from an oscillator OSC are divided down and are supplied to a ROM. The reference time data, clock pulse and frequency divided output corresponding to the stable frequency divided output outputted by this ROM are supplied and the digital reference pulses of 3 digits are outputted as the pulses for time comparison from the counter timer CTC. The synchronization of the delayed synchronizing input signal and the time of the reference pulses are compared in a pulse comparator circuit 3 formed of flip-flops FF1 to FF3 and the 3-bit discrimination outputs of logical levels H, L are generated and are latched in an output FF circuit 4. The synchronizing signal discrimination accuracy is enhanced by this constitution to make such digital processing without being affected by a fluctuation in the source voltage, etc.